Address fault detection
US12142335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Dec 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.