System and method for parallel memory test
US12142337B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Aug 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device including a controller coupled to memory components via a forward data path, and a signature register coupled to the memory components via a backward data path. The controller provides memory address signals and a controller clock signal to the memory components via the forward data path, which includes first circuitry to provide test-enable signals to the memory components that enable the memory components to read stored memory values. The backward data path includes second circuitry to receive from the memory components a set of memory signals and combine them into a combined signal. Each memory signal is associated with a respective one of the memory components and includes at least one stored memory value read from the corresponding memory component. The signature register calculates a test signature based on the combined signal and compares the test signature to an expected signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.