Semiconductor package
US12142541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2020 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Sep 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.