Efficient redistribution layer topology
US12142586B2 · kind B2 · utility
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3References
22Claims
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Key dates
| Filing date | Jun 29, 2022 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jun 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01074
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.