Multitier arrangements of integrated devices, and methods of forming sense/access lines
US12144188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2023 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.