Stepped contact within memory region
US12144263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Nov 12, 2024 |
| Priority date | — |
| Expiry date | Jan 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
A semiconductor device, such as an MRAM device, includes a stepped contact within a memory region that has a greater number of different contact structures (i.e., contact structures formed in different fabrication stages) relative to a logic region contact. The stepped contact includes a lower stepped contact and an upper stepped contact. The inclusion of the lower stepped contact allows for a relatively shorter upper stepped contact compared to the logic region contact. The stepped contact may allow the use of a multi-layer encapsulation spacer upon the sidewalls of a memory cell that fill out tight spacing therebetween, which may decrease the propensity of void formation and resulting shorting between neighboring memory cell features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.