Heterogenous-latency memory optimization
US12147351B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Apr 25, 2023 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Apr 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.