Systems, methods, and apparatuses for tile matrix multiplication and accumulation
US12147804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2021 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Jul 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.