Cross-point array IHOLD read margin improvement
US12148459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Oct 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for read in a cross-point memory array. Drive transistors pass read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to a drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.