Semiconductor memory device and control device for semiconductor memory device
US12148468B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Nov 17, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | May 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.