Mask structure, semiconductor structure and methods for manufacturing same
US12148618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Feb 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.