Semiconductor package structure having interposer substrate, and stacked semiconductor package structure including the same
US12148729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Dec 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.