Delta-sigma modulator with modified quantization error shaping
US12149252B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 12, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | May 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/235
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.