Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

US12149255B2 · kind B2 · utility

Assignee

• Shaoxing Yuanfang Semiconductor Co., Ltd. · CN

Inventors

• Raja Prabhu J · Kanchinakote, IN
• Ankit Seedher · Kanchinakote, IN
• Srinath Sridharan · Nagamangala, IN
• Rakesh Gupta · Kingsport, US
• Nitesh Naidu · Kanchinakote, IN
• Shivam Agrawal · Kanchinakote, IN
• Jeevabharathi G · Kanchinakote, IN
• Purva Choudhary · Kanchinakote, IN

Key dates

• Filing date: Jan 10, 2024
• Grant date: Nov 19, 2024
• Expiry date: Jan 10, 2044

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/24
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.