Semiconductor device with composite gate dielectric and method for preparing the same
US12150290B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 2022 |
| Grant date | Nov 19, 2024 |
| Priority date | — |
| Expiry date | Mar 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first source/drain region and a second source/drain region disposed in a semiconductor substrate. The semiconductor device also includes a word line structure disposed in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure includes a composite gate dielectric, and a lower electrode layer disposed over the composite gate dielectric. The word line structure also includes an upper electrode layer disposed over the lower electrode layer, and a graphene layer disposed between the lower electrode layer and the upper electrode layer. The composite gate dielectric includes a gate dielectric layer and a protection liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.