Apparatus and method for testing all test circuits on a wafer from a single test site
US12153087B2 · kind B2 · utility
0Cited by
0References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jun 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318511
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.