Customizable SoC state reporting
US12153487B1 · kind B1 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed computer-implemented method includes receiving, by a first circuit subsystem, a hardware error signal and storing, in response to the hardware error signal, a signal state of the first circuit subsystem in a reset-persistent register. The method also includes sending, by the first circuit subsystem, the hardware error signal to a second circuit subsystem. Various other methods, systems, and computer-readable media are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.