Non-volatile memory with optimized operation sequence
US12153801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Mar 17, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.