Patent · US Active

Power-efficient access line operation for memory

US12154613B2 · kind B2 · utility

0Cited by

1References

30Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Martin Brox · Munich, DE
Manfred Hans Plan · Hersbruck, DE

Key dates

Filing date	May 10, 2022
Grant date	Nov 26, 2024
Priority date	—
Expiry date	Nov 21, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4096
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods, systems, and devices for power-efficient access line operation for memory are described. A memory device may drive a voltage pulse on a first word line included in a set of word lines that is coupled with a master word line. The memory device may then a voltage pulse on a second word line included in the set of word lines coupled with the master word line. In between driving the voltage pulse on the first word line and driving the voltage pulse on the second word line, the memory device may maintain a voltage on the master word line below a threshold level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.