Techniques for analog multibit data representation for in-memory computing
US12154638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.