Electronic package and manufacturing method thereof, and substrate structure
US12154848B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Jul 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.