Self-aligned patterning with colored blocking and structures resulting therefrom
US12154855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2019 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Mar 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.