Damage implantation of cap layer
US12154987B2 · kind B2 · utility
0Cited by
3References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Nov 26, 2024 |
| Priority date | — |
| Expiry date | Dec 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.