Extending functionality of memory controllers in a processor-based device
US12159056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Sep 6, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.