Method of designing interconnect structure of semiconductor apparatus and method of manufacturing semiconductor apparatus using the same
US12159095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Feb 12, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of designing an interconnect structure of a semiconductor apparatus is provided. The interconnect structure includes interconnection layers sequentially stacked on a semiconductor substrate, and each of the interconnection includes dummy metal patterns and main metal patterns. The method includes: determining a layout of the main metal patterns included in each of the plurality of interconnection layers; determining a number of interconnection layers in the plurality of interconnection layers; and determining a layout of the dummy metal patterns included in each of the plurality of interconnection layers based on the determined layout of the main metal patterns and the determined number of interconnection layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.