Three-dimensional integrated system of RFID chip and super capacitor and preparation method thereof
US12159179B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Jul 28, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/13
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a three-dimensional integration system of an RFID chip and a supercapacitor and a manufacturing method thereof. The three-dimensional integration system of an RFID chip and a supercapacitor includes: a silicon substrate (200); an RFID chip (201) disposed on a front surface of the silicon substrate (200); a supercapacitor disposed on a back surface of the silicon substrate (200) at a position corresponding to the RFID chip (201), but not in contact with the RFID chip (201); through silicon via structures penetrating the silicon substrate (200) and respectively disposed on two sides of the RFID chip (201); wherein the RFID chip (201) has a chip positive electrode (2021) and a chip negative electrode (2022) electrically connected with a capacitor contact positive electrode (2131) and a capacitor contact negative electrode (2132) of the supercapacitor through the through silicon via structures on the two sides respectively; and a packaging substrate (218) electrically connected to the capacitor contact positive electrode (2131) and the capacitor contact negative electrode (2132).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.