Queue allocation in machine learning accelerators
US12159225B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Jul 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure generally provides solutions for improving the performance of a custom-built, packet-switched, TPU accelerator-side communication network. Specifically a set of solutions to improve the flow-control behavior by tuning the packet buffer queues in the on-chip router in the distributed training supercomputer network are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.