Inventor · San Diego, CA, US

Xiangyu Dong

33Patents
7h-index
35Co-inventors
65Inventor score

Filing activity: Dec 20, 2012 → May 17, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9299457B2 Kernel masking of DRAM defects Physics 42 Active
US9304913B2 Mixed memory type hybrid cache Emerging Cross-Sectional Technologies 10 Active
US9524771B2 DRAM sub-array level autonomic refresh memory controller optimization Physics 9 Active
US9911485B2 Method and apparatus for refreshing a memory cell Physics 8 Active
US9275714B1 Read operation of MRAM using a dummy word line Physics 8 Active
US8982654B2 DRAM sub-array level refresh Physics 8 Active
US9292451B2 Methods and apparatus for intra-set wear-leveling for memories with limited write endurance Physics 7 Active
US9224442B2 System and method to dynamically determine a timing parameter of a memory device Physics 5 Active
US9472257B2 Hybrid magnetoresistive read only memory (MRAM) cache mixing single-ended and differential sensing Physics 4 Active
US9431129B2 Variable read delay system Physics 4 Active
US9812222B2 Method and apparatus for in-system management and repair of semi-conductor memory failure Physics 4 Active
US9239788B2 Split write operation for resistive memory cache Physics 4 Active
US9411727B2 Split write operation for resistive memory cache Physics 3 Active
US9224452B2 Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems Emerging Cross-Sectional Technologies 3 Active
US9368187B2 Insertion-override counter to support multiple memory refresh rates Physics 2 Active
US9196339B2 Resistance-based memory cells with multiple source lines Physics 1 Active
US11704110B2 Methods for optics module firmware in-field upgrade Physics 1 Active
US9436606B2 System and method to defragment a memory Emerging Cross-Sectional Technologies 1 Active
US12014167B2 Methods for optics module firmware in-field upgrade Physics 0 Active
US9348743B2 Inter-set wear-leveling for caches with limited write endurance Physics 0 Active
US12335099B2 Enhanced reconfigurable interconnect network Electricity 0 Active
US12314753B2 Preflight checks for hardware accelerators in a distributed system Physics 0 Active
US9250998B2 Cache structure with parity-protected clean data and ECC-protected dirty data Physics 0 Active
US12159225B2 Queue allocation in machine learning accelerators Electricity 0 Active
US9230634B2 Refresh scheme for memory cells with next bit table Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.