Semiconductor package and method of manufacturing the semiconductor package
US12159826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2021 |
| Grant date | Dec 3, 2024 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a support substrate having connection wirings disposed therein. At least one capacitor is disposed on the support substrate. The capacitor has first and second electrodes that are exposed from an upper surface of the support substrate. A redistribution wiring layer covers the upper surface of the support substrate. The redistribution wiring layer has redistribution wirings electrically connected to the connection wirings and the first and second electrodes respectively. A semiconductor chip is disposed on the redistribution wiring layer. The semiconductor chip has chip pads that are electrically connected to the redistribution wirings and outer connectors disposed on a lower surface of the support substrate and electrically connected to the connection wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.