Scalable and interoperable PHYLESS die-to-die IO solution

US12159840B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Zhiguo Qian · Chandler, US
• Gerald Pasdast · San Jose, US
• Juan Zeng · San Jose, US
• Peipei Wang · Beijing, CN
• Ahmad Siddiqui · Sunnyvale, US
• Lakshmipriya Seshan · Sunnyvale, US

Key dates

• Filing date: Jun 23, 2020
• Grant date: Dec 3, 2024
• Expiry date: Nov 21, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/00014
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.