Layout method and layout apparatus for integrated circuit
US12164852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Mar 18, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout method for an integrated circuit includes the following steps: providing a layout, the layout including a first element region and a second element region, a spacing region being provided between the first element region and the second element region; and detecting whether a width of the spacing region is less than a preset width, and if yes, marking at least one of the first element region, the second element region and the spacing region, the preset width being a minimum width meeting a requirement, wherein the requirement is to fill the spacing region with at least one dummy pattern. A layout apparatus employing the layout method for the integrated circuit can quickly and accurately position a poorly-placed element region in the layout, improve the layout efficiency and layout precision of the integrated circuit, and lay a foundation for improving photolithography quality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.