Multi-bitcell structure with shared read port
US12165737B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Mar 2, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Dec 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to a device having a multi-bitcell structure with multiple bitcells. The multiple bitcells may include first port transistors and second port transistors. The first port transistors may be arranged in a P-over-N stack configuration, and the second port transistors may be arranged in an N-over-N stack configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.