Patent · US Active

Semiconductor package structure

US12165961B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

MEDIATEK INC. · TW

Inventors

Hsing-Chih Liu · Baoshan, TW
Zheng Zeng · San Jose, US
Che-Hung Kuo · Hsinchu, TW

Key dates

Filing date	Jun 6, 2023
Grant date	Dec 10, 2024
Priority date	—
Expiry date	Jun 6, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.