Modified control loop in a digital phase-locked loop
US12166494B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Feb 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.