Kannanthodath V. Jayakumar
7Patents
2h-index
3Co-inventors
36Inventor score
Filing activity: Nov 19, 2018 → Dec 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10608649B1 | Relative frequency offset error and phase error detection for clocks | Electricity | 6 | Active |
| US11018679B1 | On-chip phase-locked loop response measurement | Electricity | 5 | Active |
| US10819354B2 | Accurate and reliable digital PLL lock indicator | Electricity | 2 | Active |
| US11228403B2 | Jitter self-test using timestamps | Electricity | 2 | Active |
| US11764913B2 | Jitter self-test using timestamps | Electricity | 1 | Active |
| US12191866B2 | Linear prediction to suppress spurs in a digital phase-locked loop | Electricity | 0 | Active |
| US12166494B2 | Modified control loop in a digital phase-locked loop | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.