Three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same
US12167598B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2022 |
| Grant date | Dec 10, 2024 |
| Priority date | — |
| Expiry date | Jun 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.