Read retry method for enhancing read performance and stability of 3D NAND memory
US12169640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Aug 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a memory system for selecting from among a plurality of read retry routines based on metadata. The memory system can include one or more memory devices and a memory controller. The memory controller can also detect a failure of a read operation. The memory controller can also analyze a set of values that correspond to a set of effectors of the read operation. The memory controller can select one or more read retry routines from a plurality of read retry routines based on the analyzing. Each of the plurality of read retry routines can associated with a different effector from the set of effectors and a read voltage that corresponds to the different effector. The memory controller can also perform the selected one or more read retry routines at the portion of the one or more memory devices to negate the failure of the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.