Caching for multiple-level memory device
US12169648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Jan 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.