Hybrid resistive memory
US12170109B2 · kind B2 · utility
0Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2021 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Dec 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.