Silicon-on-insulator (SOI) circuitry for low-voltage memory bit-line and word-line decoders
US12170110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Apr 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory including a memory array having a plurality of bit-line inputs and a plurality of word-line inputs; a bit-line decoder; and a control circuit is provided. The bit-line decoder includes a first circuit and a second circuit including a plurality of low-voltage field effect transistors (FET). The control circuit provides control signals to the plurality of low-voltage FETs in a sequence of a pre-pulse phase, a pulse phase, and a post-pulse phase, wherein at the pulse phase, the first circuit and the second circuit receives a desired voltage. The control circuit provide control signals the plurality of low-voltage FETs a voltage no greater than a low-voltage at the pre-pulse phase and the post-pulse phase. In silicon-on-insulator (SOI) technologies, use of low-voltage FETs in the bit-line and word-line decoders reduces the area of the periphery circuits of the memory array without requiring change to the memory array itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.