Semiconductor memory device
US12170247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2022 |
| Grant date | Dec 17, 2024 |
| Priority date | — |
| Expiry date | Jun 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes first memory layers and second memory layers arranged in alternation in a first direction. First memory layers and second memory layers include memory strings and first wirings connected to these memory strings in common. First memory layers and second memory layers include: signal amplifier circuits electrically connected to the first wirings; second wirings connected to the signal amplifier circuits; first switch transistors connected to the second wirings; third wirings electrically connected to the second wirings via the first switch transistors; and fourth wirings electrically connected to the second wirings without via the first switch transistors. The semiconductor memory device includes: first via-contact electrodes extending in the first direction and connected to the third wirings in first memory layers; and second via-contact electrodes extending in the first direction and connected to the fourth wirings in second memory layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.