Three dimensional vertically structured electronic devices

US12170330B2 · kind B2 · utility

Assignee

• Lawrence Livermore National Security, LLC · US

Inventors

• Adam Conway · Livermore, US
• Sara Elizabeth Harrison · Livermore, US
• Rebecca J. Nikolic · Oakland, US
• Qinghui Shao · Fremont, US
• Lars Voss · Livermore, US

Key dates

• Filing date: Apr 22, 2021
• Grant date: Dec 17, 2024
• Expiry date: Jul 1, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

An apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate including a first semiconductor material, an array of three dimensional (3D) structures above the substrate, a sidewall heterojunction layer positioned on at least one vertical sidewall of each 3D structure, and an isolation region positioned between the 3D structures. Each 3D structure includes the first semiconductor material. The sidewall heterojunction layer includes a second semiconductor material, where the first and second semiconductor material have different bandgaps.