Last level cache access during non-Cstate self refresh
US12174747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Dec 20, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.