Enterprise host memory buffer for DRAM-less SSD
US12175119B2 · kind B2 · utility
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1References
20Claims
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Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Apr 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The one or more data storage devices are DRAM-less. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.