Automated translation of design specifications of electronic circuits
US12175191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2021 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Oct 14, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.