Hardware micro-fused memory operations
US12175243B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Dec 20, 2019 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.