Memory device
US12176062B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 16, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.