Semiconductor structure and manufacturing method using different ion implantation energy
US12176213B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Jul 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.