Method of forming semiconductor device using high stress cleave plane
US12176326B2 · kind B2 · utility
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46References
20Claims
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Key dates
| Filing date | Apr 10, 2023 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Apr 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implanting ions to form a cleave layer in a semiconductor device causes damage to sensitive materials such as high-K dielectrics. In a process for forming a cleave layer and repairing damage caused by ion implantation, ions are implanted through a circuit layer of a substrate to form a cleave plane. The substrate is exposed to a hydrogen gas mixture for a first time at a first temperature to repair damage caused by the implanted ions. A cleaving process may then be performed, and the cleaved substrate may be stacked in a 3DIC structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.