Photonics chips including a fully-depleted silicon-on-insulator field-effect transistor
US12176351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2022 |
| Grant date | Dec 24, 2024 |
| Priority date | — |
| Expiry date | Apr 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/8037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.